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Low Power Design ...
http://atrak.usc.edu/~massoud/Papers/LPD-talk.ps
...
http://bach.ece.jhu.edu/~etienne/ECE491/F00/slides4.ppt
Abstract EURODAC'94...
http://ballade.cs.ucla.edu/~kohcc/sigdacdrom/comp1994/euro94/abstract.htm
Table of Contents ICCAD'94...
http://ballade.cs.ucla.edu/~kohcc/sigdacdrom/comp1994/iccad94/toc.htm
Evaluation of the RTL Synthesis Tools for ...
http://bonner-pc4.rice.edu/CMS/SYN2001.pdf
EE241 - Spring 2005 ...
http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s05/Lectures/Lecture7S
Integrated Communications Design - Designing FPGA-based Internet systems...
http://cgw.pennnet.com/Articles/Article_Display.cfm?Section=Articles&SubSec
Timing Optimization of Logic Network Using Gate Duplication - Chen, Tsui (Resear...
http://citeseer.nj.nec.com/chen99timing.html
Fall 98 Presentations...
http://clpe.ece.arizona.edu/F98_presentations.htm
Power Optimization of Digital Circuits...
http://clpe.ece.arizona.edu/first_3yrs/Vrud_wang2.html
...
http://courses.cs.tamu.edu/cpsc661/walker/Slides/Logic_Synthesis_3.ppt
...
http://courses.cs.tamu.edu/cpsc661/walker/Slides/Logic_Synthesis_4.ppt
Timing Optimization of Logic Network Using Gate Duplication...
http://csdl.computer.org/comp/proceedings/asp-dac/1999/2329/00/23290233abs.
Decomposition and technology mapping of speed-independent circuits using Boolean...
http://csdl.computer.org/comp/proceedings/iccad/1997/8200/00/82000220abs.ht
Timing Driven Gate Duplication: Complexity Issues and Algorithms...
http://csdl.computer.org/comp/proceedings/iccad/2000/2238/00/22380447abs.ht
ETOX™ Flash Memory Technology: Scaling and Integration Challenges...
http://developer.intel.com/technology/itj/2002/volume06issue02/art03_flashm
Logic Optimization of Unidirectional Circuits with Structural Methods...
http://doi.ieeecomputersociety.org/10.1109/OLT.2001.937816
Technology Mapping ...
http://emicroelectronics.free.fr/onlineCourses/technomapping.pdf
KATZ_0201308576_MF.fm Page i Tuesday, November 16, 2004 8:05 PM ...
http://esminfo.prenhall.com/engineering/katz/closerlook/pdf/KatzBoriello_Pr
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http://gunther.smeal.psu.edu/13930.html
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http://gunther.smeal.psu.edu/srivastava00complexity.html
HDL Planet's Synthesis Page...
http://hdlplanet.tripod.com/synthesis/synthesis.html
...
http://humanresources.web.cern.ch/Humanresources/external/training/tech/spe
IC Design Tools ...
http://humanresources.web.cern.ch/Humanresources/external/training/tech/spe
Complexity Bounds for Lookup Table ...
http://ipdps.eece.unm.edu/2000/raw/18000953.pdf
Embedded Synthesis ...
http://klabs.org/richcontent/MAPLDCon98/Papers/a3_curtis.pdf
...
http://klabs.org/richcontent/MAPLDCon98/Papers/a3_curtis.ppt
...
http://mwnl.snu.ac.kr/~schoi/Courses/201/Course_Materials/9.CH09.rev.ppt
WHITE PAPER ...
http://nanometer.cadence.com/pdf/4064_NanometerWP_fnlv2.pdf
UC San Diego ECE 260B Home Page: fall 1999...
http://paradise.ucsd.edu/class/ece260b/
...
http://splish.ee.byu.edu/bib/complete.bib
International Conference and Workshop: Telecommunications and Mobile Computing, ...
http://tcmc.tugraz.at/PDF/tcmc2001/pdf/2_2/Kamand.pdf
...
http://uhavax.hartford.edu/ILUMOKANW/Optest1.ppt
...
http://users.ece.gatech.edu/~hamblen/book/train.acf
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http://velox.stanford.edu/papers/ESSCIRC_02.pdf
3 ...
http://vig.pearsonptr.com:8081/samplechapter/0130619701.pdf
No Title...
http://www-cad.eecs.berkeley.edu/HomePages/alberto/pubslast/pubslast.html
1...
http://www-cad.eecs.berkeley.edu/~brayton/Pubs1961-2002%20by%20topic.htm
266 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM...
http://www-eda.eit.uni-kl.de/eis/research/publications/papers/tcad97.pdf
Presentation of Labs of course 658 by Thomas Kunkel...
http://www-unix.ecs.umass.edu/~tkunkel/l1logic.html
Application Note 36 Designing with FLEX 8000 Devices ...
http://www.altera.com/literature/an/an036_02.pdf
Amazon.com: Books: Logic Synthesis for Field-Programmable Gate Arrays (The Kluwe...
http://www.amazon.com/exec/obidos/ASIN/0792395964/
WHITE PAPER ...
http://www.cadence.com/whitepapers/4064_NanometerWP_fnlv2.pdf
ECE - 756 Schedule (Spring 2000 Semester)...
http://www.cae.wisc.edu/~ece756/756schedule.html
CommsDesign - Down to the wire -- requirements for nanometer design implementati...
http://www.commsdesign.com/showArticle.jhtml?articleID=16505500
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http://www.commsdesign.com/showArticle.jhtml?articleID=16506114
Pre-Physical Design Analysis and Optimization of Repeaters Based on ...
http://www.comppub.com/publications/MSM/2000/pdf/M41.06.pdf
Program Decision Logic Optimization Using ...
http://www.crhc.uiuc.edu/ece411/sp02/papers/00964444.pdf
CS 294-7 Project 2: Placement & Routing Optimizer for Garp...
http://www.cs.berkeley.edu/~eylon/cs294-7
386 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM...
http://www.cs.bris.ac.uk/~pradhan/DownloadPapers/LOT_IEEECAD_98.pdf
...
http://www.cs.caltech.edu/courses/cs137/2004/winter/slides/day1.ppt
...
http://www.cs.caltech.edu/~andre/courses/EDA/slides/day1.ppt
Extraction of Gate Level Models from Transistor Circuits ...
http://www.cs.cmu.edu/~bryant/pubdir/iccad91.pdf
Extraction of Gate Level Models from Transistor Circuits ...
http://www.cs.cmu.edu/~bryant/pubdir/iccad91.ps
Suraj and Vikas' 760 Project II...
http://www.cs.cmu.edu/~ssudhir/760Web
Nanocell Optimization Techniques...
http://www.cs.duke.edu/~rodger/curious/pages/dolinsky/opt.html
...
http://www.cs.nthu.edu.tw/~tingting/logic/ch8.ppt
FPGA-bak...
http://www.cs.ucla.edu/~bkchoi/bib/FPGA.html
Topics Sources of delay ...
http://www.cs.ucr.edu/cs168/cs168-04win/lectures/lecture11.pdf
...
http://www.csc.uvic.ca/~csc485c/postings/slides/Logic_Synthesis.ppt
...
http://www.cse.ucsc.edu/~sojung/publication.html
Introduction...
http://www.csee.umbc.edu/~plusquel/vlsi/slides/chap5_1.html
...
http://www.csie.nctu.edu.tw/~mfchang/dgt-lab/lab-4/fpga-Spartan-2003.ppt
37th DAC Session 6, Tuesday...
http://www.dac.com/37th/ses-6.html
( ESNUG 410 Item 1 ) -------------------------------------------- [04/02/03]...
http://www.deepchip.com/items/0410-01.html
DeepChip: ESNUG Post 0164: ( ESNUG 164 Item 1 ) --------------------------------...
http://www.deepchip.com/posts/0164.html
Chapter Review...
http://www.di.ufpb.br/jose/chapter03.doc6.html
Timebase Performance Optimization...
http://www.easystreet.com/~rhayward/more_mgc.htm
COURSE TITLE: ECE 303 Advanced Digital Logic Design...
http://www.ece.northwestern.edu/courses/303.html
...
http://www.ece.northwestern.edu/~haizhou/ece303.html
COURSE TITLE: ECE 303 Advanced Digital Logic Design...
http://www.ece.nwu.edu/courses/303.html
The Impact of Pipelining on Energy per Operation in ...
http://www.ece.ubc.ca/~stevew/papers/pdf/fpl04.pdf
GATE AND THROUGHPUT OPTIMIZATIONS FOR ...
http://www.ece.umr.edu/~smithsco/dissertation.pdf
Performance Driven Synthesis for Pass-Transistor Logic ...
http://www.ece.utexas.edu/~adnan/publications/ptl-timing-iwls-98.ps
Basic Model: Hardware ...
http://www.ece.utexas.edu/~adnan/syn-03/multilevel-intro-4.pdf
866 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM...
http://www.ecs.umass.edu/ece/labs/vlsicad/papers/bds-tcad02.pdf
...
http://www.ecs.umass.edu/ece/labs/vlsicad/slides/PTLsyn.ppt
Focus GROUPs Report -- Leon Stok, IBM TJ Watson Research Center...
http://www.ee.princeton.edu/~sharad/focus.html
Domino Logic Synthesis Using Complex Static Gates ...
http://www.ee.washington.edu/research/vlsilab/thorp/ICCAD98.ps
Design and Synthesis of Monotonic Circuits ...
http://www.ee.washington.edu/research/vlsilab/thorp/ICCD99.ps
Design Rewiring Using ATPG ...
http://www.eecg.toronto.edu/~veneris/itc02.2.pdf
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, V...
http://www.eecg.toronto.edu/~veneris/tcad02.pdf
ATPG Driven Logic Synthesis for Area and Power Minimization ...
http://www.eecg.utoronto.ca/~veneris/latin01.ps
Monarch: A Platform for Logic Optimization ...
http://www.eecg.utoronto.ca/~veneris/latw4.pdf
Physical RTL optimization solves problems early...
http://www.eedesign.com/article/printableArticle.jhtml?articleID=16506114
EEDesign.com - Physical RTL optimization solves problems early...
http://www.eedesign.com/design_library/OEG20021115S0060
Log on in eetasia.com, keeping ahead of the curve of electronics design...
http://www.eetasia.com/ART_8800338062_499481,499485.HTM.1221e43b
Monterey, Synopsys lift veil on their physical-design tools...
http://www.eetimes.com/printableArticle?doc_id=OEG20000414S0048
ESA '03 International Conference ...
http://www.engr.newpaltz.edu/~bai/Research/mlpd03_rakish.pdf
Circuit Optimization...
http://www.equars.com/~marco/poli/phd/node59.html
IBM Journal of Research and Development: Standard-cell-based design methodology ...
http://www.findarticles.com/p/articles/mi_qa3751/is_199707/ai_n8770972
faq1...
http://www.geocities.com/abel_mutlu/faq1.htm
Ankur Srivastava...
http://www.glue.umd.edu/~ankurs/publist.htm
SHACKLEFORD ET AL. SASIMI 2000, Kyoto April 6-7, 2000 ...
http://www.hpl.hp.com/speeches/techtalks/2000/shackleford_paper.apr00.pdf
...
http://www.icims.csl.uiuc.edu/~sojung/publication.html
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 20, 1231-1238 (2004) ...
http://www.iis.sinica.edu.tw/JISE/2004/200411_12.pdf
Incorporating leakage current considerations in logic synthesis...
http://www.imm.dtu.dk/~s973396/project.php
Optimization of Combinational and Sequential Logic Circuits for Low ...
http://www.inesc-id.pt/pt/indicadores/Ficheiros/1924.pdf
International Workshop on Logic & Synthesis 2002...
http://www.informatik.uni-trier.de/~ley/db/conf/iwls/iwls2002.html
3 ...
http://www.informit.com/content/images/chap3_0130619701/elementLinks/chap3_
Power, Delay, and Area Constrained Synthesis for Mixed ...
http://www.lems.brown.edu/~song/synthesisreport.pdf
Table of Contents...
http://www.lsi-cad.com/LSV/toc.html
Tsutomu Sasao - Logic Synthesis and Optimization...
http://www.lsi-cad.com/sasao/logicsyn.html
LSI Logic Physical RTL Optimization (LSI PRO) ...
http://www.lsilogic.com/files/docs/techdocs/asics/VU53L2SN.pdf
Magma Design Automation, Inc. - Why Yesterday's Synthesis Tools Can't Handle Tod...
http://www.magma-da.com/c/@ECBVT9uha4atI/Pages/YesterdaysSynthesis.html
COM 501...
http://www.msrsas.org/msccontents/vsd510.htm
alberto Home Page...
http://www.parades.rm.cnr.it/~alberto/biblio.html
Home Page di alberto...
http://www.parades.rm.cnr.it/~alberto/it/biblio.html
Pericom - Products - Interface Logic - Main Page...
http://www.pericom.com/products/logic/index.php
...
http://www.princeton.edu/~wolf/EE462/Overheads/CHAP4-4.ppt
...
http://www.princeton.edu/~wolf/EE462/Overheads/CHAP4-8.ppt
QAN4 ...
http://www.quicklogic.com/images/appnote04.pdf
...
http://www.reed-electronics.com/ecnmag/index.asp?layout=articlePrint&articl
EDN - Programmable-logic directory - 8/30/2001 - EDN - CA152730...
http://www.reed-electronics.com/ednmag/index.asp?layout=article&articleId=C
IBM Research Projects Synthesis Publications...
http://www.research.ibm.com/da/logicpubs.html
RC ...
http://www.research.ibm.com/da/publications/RC20533.pdf
Efficient Logic Optimization Using Regularity Extraction ...
http://www.research.ibm.com/da/publications/regularity.pdf
:: Sequence Design :: Power Theater - Low Power Design&Power Analysis For Nanome...
http://www.sequencedesign.com/2_solutions/2a_powerdatasheet.html
An ECL Logic Synthesis System...
http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac91/papers/1991/dac9
On the Optimization Power of Redundancy Addition and ...
http://www.sigda.org/Archives/ProceedingArchives/Iccad/Iccad2001/papers/200
...
http://www.sigda.org/ispd2004/1999/slides/ispdstuff/ispdslides/synlayoutpan
ICCD 1993...
http://www.sigmod.org/dblp/db/conf/iccd/iccd1993.html
Lecture 5: ...
http://www.stanford.edu/class/ee271/handouts/lect.05.pdf
lectures...
http://www.stanford.edu/class/ee271/lectures.html
Synopsys Design Compiler -- Whitepaper...
http://www.synopsys.com/products/logic/dc98_bckgr.html
Synopsys Design Compiler Technology Backgrounder...
http://www.synopsys.com/products/logic/design_comp_tb.html
Synopsys HDL Compiler -- Overview...
http://www.synopsys.com/products/logic/hdl_comp_cs.html
Synopsys HDL Compiler -- Datasheet...
http://www.synopsys.com/products/logic/hdl_comp_ds.html
Synplicity:...
http://www.synplicity.com/events/date05/product_demo.html
TechOnLine - Current Chip Design Flow is Flawed...
http://www.techonline.com/community/ed_resource/feature_article/22966
TechOnLine - Current Chip Design Flow is Flawed...
http://www.techonline.com/community/related_content/22966
TechOnLine - Current Chip Design Flow is Flawed...
http://www.techonline.com/community/tech_group/soc/22966__DV6429895387KJ
tele-TASK - Archive...
http://www.tele-task.de/player/embedded.php
Theseus Logic - Design Flow...
http://www.theseus.com/_DesignFlow.htm
Logic Optimization of Unidirectional Circuits ...
http://www.uc3m.es/uc3m/dpto/IN/dpin08/ioltw_2001_b.pdf
ATPG-BASED PERFORMANCE AND AREA OPTIMIZATION ...
http://www.ucop.edu/research/micro/96_97/96_038.pdf
Post-Layout Logic Restructuring for Performance Optimization ...
http://www.ucop.edu/research/micro/97_98/97_028.pdf
Design of VLSI Systems...
http://www.vlsi.wpi.edu/webcourse/ch07/ch07.html
IWLS 2000 Program...
http://www1.cs.columbia.edu/~nowick/iwls-2002/www2000/program.html
Chapter Review...
http://www2.ele.ufes.br/~ailson/digital2/cld/chapter3/chapter03.doc6.html
Combinational Logic Word Problems...
http://www2.ele.ufes.br/~ailson/digital2/cld/chapter4/chapter04.doc3.html
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