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  • ...
    http://appsrv.cse.cuhk.edu.hk/~ceg3490/note/chapter3.doc

  • Tim's IRSIM-9.7 Information Page...
    http://bach.ece.jhu.edu/~tim/programs/irsim/irsim.html

  • IRSIM - Help - Manual Pages - irsim...
    http://bear.cwru.edu/eecs_cad/man_irsim.html

  • Simulation & TestBench ...
    http://cadlab.ece.ucsb.edu/ece156A_03/lec04.pdf

  • Caltech Computer Science Technical Reports - Switch-Level Fault Simulation of MO...
    http://caltechcstr.library.caltech.edu/345/

  • Caltech Computer Science Technical Reports - The MOSSIM Simulation Engine Archit...
    http://caltechcstr.library.caltech.edu/373/

  • A Switch Level Fault Simulation Environment...
    http://csdl.computer.org/comp/proceedings/dac/2000/2428/00/24280780abs.htm

  • A fault model for switch-level simulation of gate-to-drain shorts...
    http://csdl.computer.org/comp/proceedings/vts/1996/7304/00/73040414abs.htm

  • Defect-Based Test: A Key Enabler for Successful Migration to Structural Test...
    http://developer.intel.com/technology/itj/q11999/articles/art_6g.htm

  • A Multiple-Dominance Switch-Level Model for Simulation of Short Faults...
    http://doi.ieeecomputersociety.org/10.1109/ICCAD.1995.480202

  • A fault model for switch-level simulation of gate-to-drain shorts...
    http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510887

  • Mapping switch-level simulation onto gate-level hardware accelerators...
    http://dx.doi.org/10.1145/127601.127668

  • Exploiting parallelism in a switch-level simulation machine...
    http://dx.doi.org/10.1145/318013.318018

  • VItae...
    http://ece-www.colorado.edu/~lightner/IEEE/vita.html

  • Advanced VLSI Design Techniques and Tools...
    http://ece.wpi.edu/~leblebic/grad.html

  • An Integrated Core Sequence in Digital Computation...
    http://fie.engrng.pitt.edu/fie95/2a6/2a61/2a61.htm

  • A Survey on Parallel Logic Simulation (eBizSearch)...
    http://gunther.smeal.psu.edu/2410.html

  • Switch-Level Test Generation of Competing Bridging Faults in the Presence of Fee...
    http://gunther.smeal.psu.edu/3144.html

  • Analog Integrated Circuits and Signal Processing, 29, 127­149, 2001 ...
    http://kona.ee.pitt.edu/pittcad/PDF/ALOG.pdf

  • Sorting ...
    http://lambda.cs.yale.edu/cs424/notes/l11-2.pdf

  • Architecture des Ordinateurs I Abstraction Levels for Simulation ...
    http://lapwww.epfl.ch/courses/archord1/Simulation%20and%20Synthesis.pdf

  • [Gnucap-devel] Logic device (U) and switch level simulation...
    http://lists.gnu.org/archive/html/gnucap-devel/2003-09/msg00000.html

  • Lluis Ribas' research... or so ;-)...
    http://microelec.uab.es/ribas/research

  • dpp_phy...
    http://microsys6.engr.utk.edu/~bernadeta/651/dpp_phy.htm

  • ncstrl.mit.edu Digital Library Index Page...
    http://ncstrl.mit.edu/RobotBait/1132

  • Appendix One...
    http://nppp.jpl.nasa.gov/asic/Appendix.1.html

  • Section Two: Chapter Five...
    http://nppp.jpl.nasa.gov/asic/Sect.2.5.html

  • Verilog - accelerating digital design ...
    http://oldeee.see.ed.ac.uk/~gerard/VLSI/verilog.ps

  • Appendix One...
    http://parts.jpl.nasa.gov/asic/Appendix.1.html

  • Section Two: Chapter Five...
    http://parts.jpl.nasa.gov/asic/Sect.2.5.html

  • Maisie Models...
    http://pcl.cs.ucla.edu/projects/maisie/models.html

  • PARSEC: A Discrete-Event Simulation Environment for Scalable Systems...
    http://pcl.cs.ucla.edu/projects/mirsim/wamis.html

  • Western Research Laboratory - Compaq...
    http://research.compaq.com/wrl/techreports/abstracts/92.5.html

  • Western Research Laboratory - Compaq...
    http://research.compaq.com/wrl/techreports/abstracts/TN-40.html

  • Caltech Computer Science Technical Reports - Switch-Level Fault Simulation of MO...
    http://resolver.caltech.edu/caltechCSTR:1984.5132-tr-84

  • Final Project Report...
    http://seniord.ee.iastate.edu/may9900/final_report.html

  • Mark T. Smith Ph.D. ...
    http://users.ece.gatech.edu/~mts/vita_mark_smith.pdf

  • ANALYSIS OF POWER SUPPLY NETWORKS ...
    http://velox.stanford.edu/papers/ds_thesis.pdf

  • PIECEWISE LINEAR MODELS FOR ...
    http://velox.stanford.edu/papers/rk_thesis.pdf

  • Simulation 1 ...
    http://web.doe.carleton.ca/~pavan/5704Y/resources/simulation_slides-handout

  • Digital Systems Verification ...
    http://www-cad.eecs.berkeley.edu/~nardi/EE219A/lectures/lec13_bw_2xp.pdf

  • ...
    http://www-db.stanford.edu/TR/CSL-TR-91-468.html

  • Research...
    http://www-micrel.deis.unibo.it/~michele/research.html

  • CSIX Level 1 Monitor Data Sheet ...
    http://www.0-in.com/pdf_files/CSIX_L1.pdf

  • Aldec Performance Guide ...
    http://www.aldec.com/Riviera/riviera_performance_guide.pdf

  • Mixed-Mode Simulation and Analog Multilevel Simulation...
    http://www.aplac.hut.fi/courses/pc99fall/main.html

  • TECHNICAL PAPER ...
    http://www.cadence.com/whitepapers/equivalence_checking_WP.pdf

  • Publications...
    http://www.ce.chalmers.se/staff/dahlis/Publications.html

  • Research...
    http://www.ce.chalmers.se/staff/dahlis/Research_Area.html

  • MODELING A NEW RTL SEMANTICS IN C++ ...
    http://www.cecs.uci.edu/~szhao/iscas02-zhao.pdf

  • Sequential circuit test...
    http://www.cerc.utexas.edu/~jaa/testing/genetic.html

  • Ptolemy simulation of the ATLAS level-2 trigger...
    http://www.cern.ch/wheeler/ptolemy/backupnote/ptolemyDoc.html

  • Ptolemy simulation of the ATLAS level-2 trigger ...
    http://www.cern.ch/wheeler/ptolemy/ptolemyDoc.pdf

  • CommsDesign - Complex memories: the art of mixing traditional simulation with in...
    http://www.commsdesign.com/showArticle.jhtml?articleID=16500790

  • CommsDesign - Memory overwhelms current verification techniques...
    http://www.commsdesign.com/showArticle.jhtml?articleID=16500796

  • Parameter Extraction for a Microwave Micromachined Switch ...
    http://www.comppub.com/publications/MSM/99/pdf/M3303.pdf

  • Brown CS: Tech Report CS-89-07...
    http://www.cs.brown.edu/publications/techreports/reports/CS-89-07.html

  • Extraction of Gate Level Models from Transistor Circuits ...
    http://www.cs.cmu.edu/~bryant/pubdir/iccad91.pdf

  • Formal Verification of Memory Circuits ...
    http://www.cs.cmu.edu/~bryant/pubdir/tcad91.pdf

  • No Title...
    http://www.cs.cmu.edu/~bryant/vitae-full.html

  • Randal E. Bryant ...
    http://www.cs.cmu.edu/~bryant/vitae-full.pdf

  • ...
    http://www.cs.huji.ac.il/course/2003/vlsid/VLSI_10.ppt

  • No Title...
    http://www.cs.nyu.edu/web/Research/Theses/you_yongtao.html

  • Distributed Packet-Level Simulation for BGP Networks ...
    http://www.cs.rpi.edu/~szymansk/papers/scsc04.pdf

  • System Verification Using Multilevel Concurrent Simulation ...
    http://www.cs.tufts.edu/~karen/papers/lentz-micro.ps

  • Trace-driven System-level Power Evaluation of System-on-a-chip Peripheral Cores...
    http://www.cs.ucr.edu/~vahid/pubs/aspdac01_trace

  • CS@UGA: Research groups...
    http://www.cs.uga.edu/research/Researchgroups.htm

  • The Avalanche Myrinet Simulation Package ...
    http://www.cs.utah.edu/techreports/1996/pdf/UUCS-96-010.pdf

  • 37th DAC Session 48, Thursday...
    http://www.dac.com/37th/ses-48.html

  • DFTSimuLab...
    http://www.dftsimulab.com/products/main.html

  • SWITCH...
    http://www.drlevel.com/capacitance_switch.htm

  • Cadence switch-level simulation with IRSIM...
    http://www.ece.iit.edu/~vlsi/cadence/irsim/

  • Verilog Digital System Design ...
    http://www.ece.neu.edu/info/verilog/class/actual/IntroVerilog.pdf

  • Student Projects...
    http://www.ece.neu.edu/research/navabi/Actual/student_projects.htm

  • EE360R Summer'03 Scott Fehr/Seokjin Lee/Kyoil Kim ...
    http://www.ece.utexas.edu/~sfehr/FinalCoverage.pdf

  • Validation Approach Through an Example...
    http://www.ececs.uc.edu/~ddel/projects/dss/dac93/node5.html

  • Experimental Results...
    http://www.ececs.uc.edu/~ddel/projects/pdss/proposal/node12.html

  • VIUF Proceedings -- SPRING 1993...
    http://www.eda.org/VIUF_proc/Spring93/abstract_spring93.html

  • EDACafe: ASICs .. the Book...
    http://www.edacafe.com/books/ASIC/Book/CH13/CH13.9.php

  • Delay measurement with RC model ...
    http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/notes/Lecture%209%20-%20Ci

  • EE4 & MSc course on ASIC Design...
    http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/

  • ...
    http://www.ee.kent.ac.uk/chipwise/cwtutor/ChipWiseWbk.doc

  • ...
    http://www.ee.ttu.edu/ee/Cadence/CommonDirectory/Final%20Tutorials/Simulati

  • Logic Simulation with Verilog...
    http://www.ee.vt.edu/~ha/cadtools/cadence/verilog.html

  • Research NDR Group: Power Estimation and Reduction...
    http://www.eecs.umich.edu/~shriram/group/pages/power.html

  • EEDesign.com - Designers stand up for gate-level simulation...
    http://www.eedesign.com/isd/OEG20031216S0018

  • EEDesign.com - Verplex spins equivalence checker for embedded memories...
    http://www.eedesign.com/story/OEG20030210S0034

  • EEDesign.com - Designers stand up for gate-level simulation...
    http://www.eedesign.com/story/OEG20031216S0018

  • Switch Level Simulator...
    http://www.elektroda.pl/eboard/sutra176671.html

  • find "Switch-Mode Power Supply SPICE Simulation Cookboo...
    http://www.elektroda.pl/eboard/sutra94727.html

  • ...
    http://www.eng.auburn.edu/department/ee/mgc/lsim/lsim.html

  • ECE 488 Advanced Computer Architecture...
    http://www.eng.kuniv.edu.kw/~abet/CE%20464-rev.htm

  • comp.lsi.cad Frequently Asked Questions With Answers (Part 3/4) [LONG]...
    http://www.faqs.org/faqs/lsi-cad-faq/part3

  • comp.lsi.cad Frequently Asked Questions With Answers (Part 4/4) [LONG]...
    http://www.faqs.org/faqs/lsi-cad-faq/part4/

  • comp.lsi.cad Frequently Asked Questions With Answers (Part 4/4) [LONG]...
    http://www.faqs.org/faqs/lsi-cad-faq/part4

  • Patent 4695968: Digital system simulation method and apparatus having improved s...
    http://www.freepatentsonline.com/4695968.html

  • Re: gEDA: What switch level simulator to use?...
    http://www.geda.seul.org/mailinglist/geda-dev69/msg00095.html

  • ...
    http://www.harvardpr.com/home/article_details.asp?id=5841

  • To be published in proceedings of MASCOT2003 ...
    http://www.hcs.ufl.edu/pubs/MASCOTS2003.pdf

  • Network Components for Ptolemy v0.6 20 Oct 99 ...
    http://www.hep.man.ac.uk/~rich/ptolemy/nework_simulation_v06.pdf

  • D E C E M B E R 1 9 9 2 ...
    http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-32.pdf

  • D E C E M B E R 1 9 9 3 ...
    http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-40.pdf

  • IAIK IAIK ...
    http://www.iaik.tu-graz.ac.at/teaching/05_vlsi-design/slides/04_designflow.

  • ICCAD 2001...
    http://www.iccad.com/2001/cfp.html

  • ICCAD 2002...
    http://www.iccad.com/2002/cfp.html

  • Efficient Usage of Concurrency Models in an Object-Oriented Co-design ...
    http://www.ics.uci.edu/~skshukla/concur/garg_date01.pdf

  • Simulation ...
    http://www.ida.liu.se/~zebpe/heuristic/simulation.pdf

  • ICCAD 1990...
    http://www.informatik.uni-trier.de/~ley/db/conf/iccad/iccad1990.html

  • DBLP: Randal E. Bryant...
    http://www.informatik.uni-trier.de/~ley/db/indices/a-tree/b/Bryant:Randal_E

  • Pro Products -- Multisim 7 Verilog Simulation...
    http://www.interactiv.com/html/proprodg11b.html

  • A Switch-Level Simulation Method based on Event Driven Algorithm...
    http://www.ipsj.or.jp/members/SIGNotes/Eng/03/1989/048/article004.html

  • LCS Publication - MIT-LCS-TR-259...
    http://www.lcs.mit.edu/publications/specpub.php?id=827

  • S u c c e s s S t o r y ...
    http://www.nassda.com/SAN_Success_Story_5.17_r2.pdf

  • intro...
    http://www.ntu.edu.sg/home/exzhou/Research/XSIM/

  • Powell's Books - Verilog HDL 2ND Edition by Samir Palnitkar...
    http://www.powells.com/cgi-bin/product?isbn=0130449113

  • IP.com's Prior Art Database...
    http://www.priorartdatabase.com/IPCOM/000007619

  • by Z. Barzilai ...
    http://www.research.ibm.com/journal/rd/285/ibmrd2805H.pdf

  • Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors...
    http://www.research.ibm.com/journal/rd/414/shepard.html

  • MAGIC/IRSIM Notes...
    http://www.reservoir.com/extra/ee425/roadmaps/irsim.html

  • Computer Aids for VLSI Design...
    http://www.rulabinsky.com/cavd/text/chap06-3.html

  • Computer Aids for VLSI Design...
    http://www.rulabinsky.com/cavd/text/chap06-4.html

  • EE560: Lab 3...
    http://www.seas.upenn.edu/~ee560/lab/lab2_new.html

  • A Switch Level Fault Simulation Environment ...
    http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac2000/papers/2000/da

  • ACCELERATING SWITCH-LEVEL SIMULATION BY FUNCTION CACHING...
    http://www.sigda.org/Archives/ProceedingArchives/Dac/Dac91/papers/1991/dac9

  • .:: SIMUCAD ::....
    http://www.silos.com/verilog_press_releases/verilog_press95b.shtml

  • .:: SIMUCAD ::....
    http://www.simucad.com/verilog_press_releases/verilog_press95b.shtml

  • .:: SIMUCAD ::....
    http://www.simucad.com/verilog_press_releases/verilog_press95c.shtml

  • Static Free Software: Specifications...
    http://www.staticfreesoft.com/electricSpecsTools.html

  • Synopsys Products - Former InnoLogic Systems: Sun Case Study...
    http://www.synopsys.com/products/acmgr/innlo/casestudy/suncase.html

  • Success Story ...
    http://www.synopsys.com/products/esp/sun_ss.pdf

  • Simulation of non-classical Faults on the Gate Level1 ...
    http://www.tet.uni-hannover.de/papers/1993/93jalt.pdf

  • Textbookx : Product Detail...
    http://www.textbookx.com/product_detail.php?affiliate=DirectTBX&detail_isbn

  • Complex memories: the art of mixing traditional simulation with innovative verif...
    http://www.us.design-reuse.com/articles/article5406.html

  • Memory overwhelms current verification techniques...
    http://www.us.design-reuse.com/articles/article5412.html

  • linux software and linux documentation for all your needs : usinglinux.org...
    http://www.usinglinux.org/man/irsim.1.html

  • Instruction-Set Simulation and Tracing...
    http://www.xsim.com/bib/index1.d/Index.html

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